BUSES AND CONTROLLERS( N6 j1 u2 `+ U2 T- c
      6 ~% w; x, W% x* _. H7 ~
　　The first two I/O tasks noted in Section 1-5 concern the establishment of connections between the memory and the I/O devices and the control of data transfers over this connection．Most modern computers use a bus，or buses，for interconnecting the major components of the system．A bus serves as a pathway between components for passing address，instructions，and data．A simple high-level view of a bus is shown in Fig. 1-17．This is the bus shown in Fig. 1-16 that is used with the coprocessor I/O．This bus interconnects the processor，main memory，and I/O devices by means of their controllers．

　　Buses can be classified in a number of ways：by purpose，control，and communication technique．5 ^' N- `. K! N% n6 a
    ( ]  ~& N" @; g  \0 l( s+ }
　　1．Dedicated or general purpose
5 Y7 y' q9 [! r- o　　The major difference between dedicated and general-purpose buses is that a dedicated bus is point-to-point between two physical devices，whereas a general-purpose bus interconnects more than two physical devices．Fig. 1-18 illustrates the two types．Dedicated buses are used in cases in which the latency and the bandwidth requirements are such that sharing the bus with another user can result in unacceptable system performance．[1]  Note that a dedicated bus does not need address lines because the source and destination are addressed by implication．That is，device 1 always sends to device 2 or device 2 to device 1．Some dedicated buses are unidirectional with information flow in only one direction．For example，the bus that connects a memory to a graphics controller may be unidirectional。
6 }( C3 t) U( h/ a+ v　　Because dedicated buses are used internal to the processor or for special high-bandwidth applications without general-purpose capabilities，these buses are not considered further．Instead，the following paragraphs discuss the control and communications design techniques found with general-purpose buses．
  {2 a' b: D- A5 d4 ~

　　 Also，with a general-purpose bus，a number of users share the same bus and simultaneous requests for the bus are resolved by one of a number of resolution techniques．Some of the devices on a general-purpose bus are both senders and receivers or only senders or only receivers．For example，a printer controller’s primary function is to receive data and send some status information．A disk controller，on the other hand，sends and receives data and sends status information．. {/ a1 [* _% r4 V/ c+ p
　　总线和控制器
# }/ D! {" z; ]2 i- ^: m" y   + \9 Y) N% Y$ C0 b6 X+ V
　　第1. 5节提到I/O的前两个任务是在存储器和I/O设备之间建立连接并在这种连接上控制数据的传送。大多数现代计算机用一条或多条总线连接系统的各主要部件。总线的作用是为各个部件之间传送地址、指令和数据提供通路。图1-17是总线的高层简单视图。这是图1-16中用于协处理器I/O的总线。这一总线由控制器将处理器、主存储器和I/O设备连在一起。9 `3 |/ b5 F8 g9 l. T1 o
　　总线可以按多种方式分类，即按目的，按控制方法和按通信技术分类。
6 p  N6 Z2 ]/ g9 d2 ]　　1．专用或通用
' R% ~1 N4 F3 x( r# A3 t　　专用与通用总线的主要区别为：专用总线是两个物理设备之间的点对点连接，而通用总线连接多于两个物理设备。图1-18展示了这两种连接类型。当与另一个用户共享总线时，如果由于等待时间和带宽要求得不到满足使系统性能下降得不能忍受时，须采用专用总线。注意，由于在专用总线中，源和目的地址是隐含的，所以不需要地址线。也就是设备1总是向设备2发送信息或相反。某些专用总线是单向的，信息流只有一个方向。例如，连接存储器和图形控制器的总线就可以是单向的。9 z2 H8 s/ |; X# ?2 t7 M
　　 由于专用总线用于处理器内部，或用于不需要通用功能的大带宽专用系统，因而我们对这些总线不做进一步讨论。相反，下面将讨论通用总线中的控制和通信设计技术。
4 ]# H: i: m8 s& O　　 同样，对于通用总线，多个用户共享同一条总线，当他们同时对总线提出请求时，可采用多种技术中的一种加以解决。通用总线上的某些设备可以既是发送器又是接收器，也可以只是发送器，或只是接收器。例如，打印机控制器的主要功能是接收数据并发送某些状态信息。而磁盘控制器既要发送和接收数据，又要发送状态信息。

2．Centralized or Decentralized Control　　The control of a general-purpose bus can be either centralized or decentralized．The basic requirement is to grant or not grant a device access to the bus．With centralized or decentralized control，all devices are treated equally except for their priority of access．Thus，if one of the devices is the processor，it may be given the highest priority for bus access．However，in some systems an I/O device may have the highest priority because of the loss in system performance；for example，if a disk is unable to read and misses a complete revolution，many milliseconds will be lost．[2]
+ I3 d+ [* U. n# @, K% x* k1 q+ t　　Centralized Control．A single hardware control unit will recognize a request and grant access to the bus to a requesting device．It is the responsibility of the controller to resolve simultaneous requests and assign priority to the requests．At least three designs are used for centralized controllers：daisy chain，polling with a global counter，and polling with local counters．
6 a2 o7 i+ x( b/ ?/ ?; T  r0 ^0 }　　Distributed Control．Distributed control，also known as decentralized control，distributes the control function between all the devices on the bus．The major advantage of decentralized control is that the system is easily expandable by the addition of modules．As with centralized control，there are three basic designs：daisy chain，polling，and independent requests．2 N7 W. z+ P  }" v: N
   
+ T* i: x" a% y5 i6 C* ]　　3．Synchronous or Asynchronous Communication5 {3 f( P  T& |
　　The transmission of addresses，control information，and data between two devices may be synchronous with a clock，or asynchronous without a clock and self-timed．
. e* x7 S/ r4 H( X! Y; X　　Synchronous Communication．A simplified diagram of a synchronous bus（the data and clock portion）connected between two devices is shown on the left of Fig. 1-19．Data are to be transmitted between the card in the right-hand slot to the card in the left-hand slot．The transmitter and the receiver are clocked from a common source on the left-hand card．
/ I* j" g! [% ~- d

　　Asynchronous Communication．Asynchronous communication for buses was developed to overcom the worst-case clock rate limitations of synchronous systems．With asynchronous communications，data transfers occur at the fastest rate and smallest delay possible under the circumstances of the physical status of the bus．As cards are added to the bus，the timing automatically adjusts for each card．There are a number of asynchronous protocols；however，only one of the simpler ones is discussed here．! \( Y( y* v3 }% y' \( I9 O
　　The timing diagram for an asynchronous exchange is shown in Fig. 1-20．This figure illustrates the action when a source sends data to a destination．* u3 `- }/ `, C

　　2．集中式或分散式控制- Z% n4 N* g4 F
　　 通用总线的控制既可以是集中式，也可以是分散式。其基本要求是授予还是不授予设备对总线的访问权。除了访问总线的优先级以外，集中式和分散式控制对待所有的设备都是一视同仁的。因此，如果设备是处理器，则应给它以总线访问的最高优先级。但是在某些系统中，为避免对系统性能的损害，让某种I/O设备具有最高优先级。例如，磁盘若转动一圈内还读不出数据，则损失很多时间。
2 c( f$ x! E/ D* f2 D　　集中式控制。用一个控制器硬件去识别总线请求并允许请求设备去访问总线。该控制器的责任是处理同时来的多个请求并对这些请求安排优先级。集中式控制器至少有3种方式：菊花链式、带全局计数器的轮询和带局部计数器的轮询。
: j0 I& K; n. H　　分布式控制。分布式控制又称分散式控制，它把控制功能分布在总线上的所有设备中。分散式控制的主要优点是通过增加模块使系统容易扩充。与集中式控制一样，分散式控制也有3种基本方式：菊花链、轮询和独立请求。
" a3 A1 M: ?  n　　3．同步或异步通信$ _9 H( T$ [# a
　　地址、控制信息和数据在两个设备之间可以用一个时钟同步传送，或不用时钟，而用自身的定时器实现异步传送。# O! G2 \/ P% X9 H) H
　　 同步通信。连接两个设备的同步总线（数据和时钟部分）简化框图如图1-19（左）所示。数据从右边槽中的卡传向左边槽中的卡。发送器和接收器用左边卡上的公共时钟源同步。- n/ a4 [9 r! e: j4 _
　　异步通信。总线的异步通信是为了克服同步系统中极差的时钟频率限制而开发的。异步通信中，数据在总线的物理状态环境下以最快的速率和最小的时延传送。当一些卡加到总线上时，会自动为每一卡调整时钟。异步协议有很多种，这里只讨论比较简单的一种。
1 `' X* @( C/ V6 s) K　　图1-20为异步交换时序图，该图说明了当发信方向接收方发送数据时的工作过程。

4．Bus Design Examples
! [8 L4 N2 j3 t. X6 s    - `8 k$ t4 P6 t. r
　　Table 1-3 provides examples of the four general-purpose bus types from the taxonomy：centralized and decentralized control and synchronous and asynchronous communications． + v8 c! r( @" }8 p
　　PCl. Q, e" J7 }- r; \. Q/ V. O, f
　　The peripheral component interconnect（PCI）is a recent high-bandwidth，processor-independent bus that can function as a mezzanine or peripheral bus．Compared with other common bus specifications，PCI delivers better system performance for high-speed I/O subsystems（e．g．，graphic display adapters，network interface controllers，disk controllers，and so on）．The current standard allows the use of up to 64 data 1ines at 33 MHz，for a raw，tansfer rate of 264 MB/s，or 2．112 Gb/s．[3]  But it is not just a high speed that makes PCI attractive．Economically，PCI is specifically designed to meet the I/O requirement of modern systems；it requires very few chips to implement and supports other buses attached to the PCI bus．9 w' [$ D" z+ ]0 V9 z

" v+ M; \2 _  F　　PCI is designed to support a variety of microprocessor-based configurations，including both single - and multiple -processor systems．Accordingly，it provides a general-purpose set of functions．It makes use of synchronous timing and a centralized arbitration scheme．$ s& d0 H/ Z9 J
　　Fig. 1-21（a）shows a typical use of PCI in a single-processor system．A combined DRAM controller and bridge to the PCI bus provides tight coupling with the processor and the ability to deliver data at high speeds．[4]  The bridge acts as a data buffer so that the speed of the PCI bus may differ from that of the processor’ s I/O capability．In a multiprocessor system（Fig. 1-21（b）），one or more PCI configurations may be connected by bridges to the processor’s system bus．The system bus supports only the processor / cache units，main memory，and the PCI bridges．Again，the use of bridges keeps the PCI independent of the processor speed yet provides the ability to receive and deliver data rapidly．[5]
7 K& t! p% ~* ~& W6 c% t* v2 J　　4．总线设计举例
* S8 X& R  M; w1 ]4 P$ s8 }+ p　　 表1-3从分类学角度给出了4种通用总线类型：集中式和分散式控制及同步和异步通信。" o: S8 U- `) x2 s0 ~% H
　　PCI" y2 {* K. ~! D, `! {: `1 _7 i+ E
　　外设部件互连（PCI）是一种近来使用的大带宽、独立于处理器的总线，可以作为底层或外围总线。与其他通用总线规范比较，PCI为高速I/O子系统（如图形显示适配器、网络接口控制器、磁盘控制器）提供更好的系统性能。现在的标准在33MHz主频时，可使用多达64条数据线，原数据传输速率可达264Mb/s，或2. 112Gb/s。PCI不仅因高传输速率而具有吸引力，它还是为满足低价位的现代系统而专门设计的；要求很少的芯片即可实现并支持与PCI总线连接的其他类型总线。
# L8 m$ T* {4 H2 p" L　　PCI支持各种基于微处理器的配置，包括单处理器系统和多处理器系统。相应地，它提供一套通用功能，并采用同步定时和集中仲裁机制。2 B( _: K; d3 z! d. }! Z# k% w) I: _
　　图1-21（a）展示了PCI在单处理器系统中的典型应用。连向PCI总线的DRAM控制器和桥接器的组合与处理器紧密耦合，具有高速数据传输能力。桥接器的作用相当于数据缓冲器，用于解决PCI总线速度与处理器I/O能力不匹配的问题。在多处理器系统中（如图1-21（b）所示）可通过桥接器把1个或多个PCI配置与处理器系统总线相连。系统总线只支持处理器-高速缓存部件、主存储器和PCI桥接器。再者，桥接器的使用让 PCI与处理器速度无关，却带来了数据接收和发送的高速度。

NOTES [1]in which引出的定语从句修饰cases，从句中又由such that引出状语从句，此从句中主语为sharing the bus．
# `) n) i; g1 X. @6 w[2]将损失很多（毫秒的）时间．( l% X% N2 l8 {* l: ?
[3]264MB/s折算为数据传输速率为264×8Mb/s=2．112Gb/s．8 N3 x( W) W+ F& Z; Z
[4]DRAM：动态随机存储器。bridge实为缓冲器，见下句．% q# C2 \# ?0 k0 w
[5]yet作“并”解，由yet引出另一个并列句．
1 A6 t5 |; C* H1 D. f
/ F2 i# F5 m) l0 E7 T7 p
6 f) U- w1 }) X% b  t9 SEXERCISES
5 o: `4 y# v# J+ b8 Y/ g: Z8 q1．True / False．
! E' T3 @0 p0 s9 J, g% }- b（1）______ A general-purpose bus is point-to-point between two physical devices．# E3 P% {9 ~9 \  |/ _, q) |2 ^
（2）______Dedicated buses are used of special high-bandwidth applications．
1 j. q1 C' a/ W6 A1 s& j（3）______ Many users on a general-purpose bus can share the same bus simultaneously．
8 v8 i. \4 p& |+ q2 P) Z（4）______ The difference between centralized and decentralized control is to grant or not grant a device access to the bus．
4 X5 X9 t2 T1 R（5)______According to this text，decentralized control is the same as distributed control．   
- k; x$ J) f0 A( G$ W（6）______The clock rate of asynchronous communication is limited．, S1 |+ i' \5 u# l
（7）______PCI is designed to support single processor system only．
3 R5 g8 g, S6 G/ d' u) ]+ g% K7 s% g（8）______ PCI bridge acts as a buffer．; k' d  j8 ~3 j0 T8 K6 h  w/ @' k
（9）______ A disk controller has a receiver only．! k7 |+ _$ k$ d/ s9 F
（10）______ A dedicated bus needs address 1ines．* a; A+ e! Y, E9 \( t
2．Fill in the blanks．
0 L2 b( ?5 k6 ]( x& v7 g（1）In a computer system the bus is used to pass______between its components．& X2 _: V" }0 k2 H+ F5 d
（2）The current standard of PCI allows the use of up to______．$ |+ z% W& \) o, U
（3）We can classify the buses by ______．
7 Z2 q1 R( {6 E5 Z9 d（4）When we hope short latent time and high bandwidth of a bus，we should choice______." ?1 g' T; ]- ?7 C
（5）Synchronous communication needs a common______while asynchronous communication doesn’t need．9 c4 M+ W, X0 Q9 g/ g+ O
（6）All devices in a centralized control are treated equally except for their ______．  ?- r' D6 p4 @5 z5 e/ R
（7）If a disk is unable to read，the system performance will be______．. H- n# A+ L2 J
（8）Centralized controllers have at least three types______．. B( r; R: |, i1 x
（9）Asynchronous transmission can get the fastest______and smallest______．  $ w7 m2 w  \9 X  {  v3 [5 W. v
（10）In a typical server system we can find two types of bus，they are______．, ^8 `; ]7 f3 i+ D5 Y
      a．64 data lines; I+ s) y5 C# u) [3 F$ f' M
      b．priority for bus access
/ K  V$ E& {, r/ n: v      c．dedicated bus0 n4 d! s. l- U) b& G  E9 w
      d．system bus，PCI bus
6 u& i( C# q& k      e．daisy chain，polling with a global counter，and polling with local counters4 s+ d3 H0 i/ ~. g* a' N$ e
      f．data rate，delay0 `& l; L" D# ^5 c* A( m8 Z
      g．clock
) R" O+ t2 M5 H& e      h．lost
9 e1 Z* C1 R* O0 Y1 D+ T$ V) P0 Y      i．address，instruction，and data6 F6 f% z0 x$ [4 r
      j．purpose，control，and communication technique
  H7 ~) {) O: W3 }* e, b( m    1.（1）f（2）t（3）t（4）f（5）t（6）f（7）f（8）t（9）f（10）f
# _& H1 ~3 ]; `( D8 Z( o    2.（1）i（2）a（3）j（4）c（5）g（6）b（7）h（8）e（9）f（10）d

READING MATERIALS
! D/ P1 v" }* o7 @                  
2 s. X4 X; }9 z1 m: C9 M　　JUST WHAT IS THE UNIVERSAL SERIAL BUS？
$ n. A6 q! T4 c  x$ D   
3 s# P0 e; J3 b4 m& I' s$ F3 r( Y　　The Universal Serial Bus is one of the fastest-growing and most widely accepted expansions to the personal computer in recent memory．It is impossible to buy an Intel-based PC（which makes up 94% of the personal-computer market）without a Universal Serial Port Bus．This is not to say that the USB is limited to the PC world，not by any stretch．Every computer hardware manufacturer is now acting to implement the Universal Serial Bus on its own platform．　　Why the sudden interest in something as seemingly trivial as a serial port? The answer is that the Universal Serial Bus is much more than a serial port一it’s a serial bus．This means that a single port on the back of your computer can be the window（no pun intended）into a myriad of devices．Devices can be daisy-chained together．Groups of devices can be separated by concentration hardware called a hub．When you think of the Universal Serial Bus，it’s best to think of it as a“network”of device，much as you would think of the Ethernet network．Fig. 1-22 illustrates what a typical network of USB devices might look like．: _4 g9 m5 c5 J- L$ _6 L% W) P" ^
　　Chaining a bunch of devices together might not seem like such a good thing at first glance．In fact，it might seem like a downright bad idea for a lot of devices to share what little bit of bandwidth serial devices have traditionally had to work with．After all，there is barely enough bandwidth on an RS-232 port to get a decent connection to a printer．There certainly isn’ t enough to talk to a digital camera to download images．
4 V! m2 j. \0 u' @　　The answer lies in providing a fast bus．We have to be careful with our terminology，though，
6 B* Z! K6 J4 x0 Mbecause the Universal Serial Bus is considered in the computer industry to be a“mid-and low-speed”bus．The Universal Serial Bus operates at over 10 million bits per second-this is the speed of the computer network in most businesses．$ u+ O0 U9 m+ A' K5 _, y

　　The Universal Serial Bus is not considered“fast”when compared to things such as the Fiber Channel serial bus，which clocks in at about 300 million bits per second，or to upcoming bus technologies such as the IEEE 1394“FireWire”bus to control audio and video sources that are“broadcast quality”．So we will accept that the USB is a“mid-speed”bus and move on．) x+ }& f4 z; s- v$ [$ n' b
　　The Universal Serial Bus was designed with the thought of providing pure digital audio，video，and telecommunications to the modern computer user．The speed of the bus is more than sufficient to support these types of devices．1 T- [7 F& ?) D$ a% J! `! Y9 p, L$ ]
　　A big problem with personal computers has always been connecting to the peripherals that you want to use．Everything always seems to need its own adapter card plugged into the bus．There are video cards for high-resolution video．There are game cards to drive your joysticks．There are sound cards to drive speakers and there are video-input cards to bring video into the computer．The list goes on and on．
7 @+ H% U, S& g" m5 W) x' H# h: X　　Computers are shrinking．Every year there are fewer slots for adapter cards．The goal of thepersonal computer industry truly is to make the computer as ubiquitous and unobtrusive as possible．At the same time，the computer now contains sufficient technology and raw“horsepower”to run the types of applications and drive the types of tasks that are requiring precision digital input and bandwidth intensive peripherals．Video conferencing on personal computers is today a reality．Surround sound stereo from your personal cornputer is a standard function．! }; _- Y5 q$ U. a
　　The computer industry is striving to enclose a technology that is expanding to the point that mid-and high-speed digital peripheral devices are required into an ever shrinking footprint．This is where the Universal Serial Bus comes into play．Just put all of the input and output to peripherals outside“the box”and don’t use any slots．Put the intelligence into the devices，rather than into the computer．
8 k. S' |7 t( b0 ?. \Peripherals designers are now freed up to implement solutions that are in“one piece”——they don’t have to split the functionality of a peripheral between a device and an interface card．This is win for them．As this happens，the internal bus on your computer ceases to be saturated with traffic and information flowing between these interface cards．This is a win for you；you’ll find that you achieve better overall system performance with this type of configuration．
# w& w8 Z$ H0 R9 J! i. U0 r0 V, Z　　Speaker designers are incorporating the functions previously performed by your sound card directly into the speaker．Video-input folks are building video digitizers to plug into the Universal Serial Bus．Even monitor manufacturers are putting Universal Serial Bus interfaces into the backs of their monitors，making the video card obsolete．There are digital joysticks that offer superhigh resolution．3 S8 @9 r% [% X
　　ASSOCIATIVE WORDS
* j7 b" q  G3 I8 e' ]$ n[Absolute address]   An address in a computer language that identifies a storage location or a device without the use of any intermediate reference．
; A. t: ^, T8 d( T- i& K2 m4 L[Accumulator]   The name of the CPU register in a single-address instruction format．The accumulator，or AC，is implicitly one of the two operands for the instruction．# L9 S8 r9 d6 V; m
[Address Space]  The range of addresses（memory，I /O）that can be referenced．6 p- ?' \/ U7 O- D8 A8 n
[Associative Memory]  A memory whose storage locations are identified by their contents，or by a part of their contents，rather than by their names or position．
7 ~3 s+ ]* F% ^( f' p2 p% @[Base Address]  A numeric value that is used as a reference in the calculation of addresses in the9 i+ y! x4 k. X  `  F
execution of a computer program．+ x! w4 b& \/ k: ^5 L5 H. v. c& w
[Buffer]  Storage used to compensate for a difference in rate of flow of data，or time of occurrence of events，when transferring data from one device to another．
8 e# `7 b7 _9 w- [3 ^3 c0 F; I[Control Storage]  A portion of storage that contains microcode．
# E& @0 F! W! l  g) D/ ]( s: R  q# v* \[Direct Address]  An address that designates the storage location of an item of data to be treated as operand．Synonymous with one-level address．
5 t) W5 q! L# Q+ T7 l/ r6 S[Direct Memory Access（DMA）]  A form of I/O in which a special module，called a DMA module，controls the exchange of data between main memory and an I/O module．The CPU sends a request for the transfer of a block of data to the DMA module and is interrupted only after the entire block has been transferred．
% }, H- F9 e( q( t+ }; l[Execute Cycle]  That portion of the instruction cycle during which the CPU performs the operation specified by the instruction opcode．/ i! P0 V8 c9 _
[Fixed-Point Representation System]  A radix numeration system in which the radix point is implicitly fixed in the series of digit places by some convention upon which agreement has been reached．4 u0 {1 \+ T! E" {' P( w
[Floating-Point Representation System]  A numeration system in which a real number is represented by a pair of direct numerals，the real number being the product of the fixed-point part，one of the numerals，and a value obtained by raising the implicit floating-point base to a power denoted by the exponent in the floating-point representation，indicated by the second numeral．( d! P5 Q$ b2 ?4 a& V
[Indexing]  A technique of address modification by means of index register．
. e& |' _3 I, b. d0 G3 o[Interrupt]  A suspension of a process，such as the execution of a computer program，caused by an event external to that process，and performed in such a way that the process can be resumed．Synonymous with interruption．; k" w6 Z. }9 i) T% ]* h5 @
[I/O Channel]  A relatively complex I/O module that relieves the CPU of the details of I/O operations．An I/O channel will execute a sequence of I/O commands from main memory without the need for CPU involvement．0 I( h" T& Y; T
[I/O Processor]  An I/O module with its own processor，capable of executing its own specialized I/O instructions or，in some cases，general-purpose machine instructions．* c4 h7 {9 s8 Q0 k' W5 Y% l; ]4 |8 }
[Microinstruction]  An instruction that controls data flow and sequencing in a processor at a more fundamental level than machine instructions．Individual machine instructions and perhaps other functions may be implemented by microprograms．7 A7 b& _- o) X$ {! b+ A
[Microprogram]  A sequence of microinstructions that are in special storage where they can be dynamically accessed to perform various functions．1 P* I4 d" E* ]$ x
[Multiprogramming]  A mode of operation that provides for the interleaved execution of two or more computer programs by a single processor．
9 y6 k3 c0 g4 `+ P5 c[Redundant Array of Independent Disks（RAID）]  A disk array in which part of the physical storage capability is used to store redundant information about user data stored on the remainder of the storage capacity．The redundant information enables regeneration of user data in the event that one of the array’s member disks or the access path to it fails．
% D+ Q& h1 M; f[Volatile Memory]  A memory in which a constant electrical power source is required to maintain the contents of memory．If the power is switched off，the stored information is lost．